The invention relates to a system for processing synchronous time-division (STD) signals as well as asynchronous time-division (ATD) data packets, in which input signals spread over various input channels are converted into output signals spread over various output channels, in response to control means the input signals being temporarily stored in a first-in first-out (FIFO) memory and read out therefrom, and are also temporarily stored in a RAM and read out therefrom as well.
A similar system is known from U.S. Pat. No. 4,612,636. In the system described in that Patent asynchronous data packets comprising each a header with a channel address for which the packet information is intended, as well as two information bytes, are stored in a FIFO (first-in first-out buffer). The header of the asynchronous data packets determines a memory location in a RAM at which the information bytes are then stored. Each memory location is coupled to a specific output channel. The RAM memory locations associated to an output channel (for example, a time channel in a multiplex signal) are read out cyclically, so that the information concerned appears on an output line as a signal, possibly in multiplex form, synchronized with other channels. The asynchronous data packets applied to the system are also spread over various channels (possibly multiplex channels). The use of a FIFO in combination with a RAM avoids that a FIFO and a control is necessary for each channel.
A drawback of the prior-art system is that it is only suitable for converting asynchronous data packets into synchronous multiplex signals, whereas there is also a need for a system converting synchronous time-division signals into asynchronous time-division data packets.